1. The power position of the pins on one side has been adjusted. V1.3 is consistent with V1.2 and is no longer compatible with V1.1 2. The model of TI power supply chip has been adjusted 3. The CLK pin of has been adjusted to SRCC clock pin (it can adapt to more IP cores) Please note: the physical slightly color difference or difference, does not affect the use, please do not mind, thank you! Board resources:Main chip 7020 ( chip industrial grade) 512MB DDR3 TF card slot A16MB QSPIFLASH (can be responsible for startup) EEPROM 2KB (PL) Two LEDs (PL) Two buttons (PL) + a POR reset button One UART (PL) One onboard XILINX downloader One USB can be used as USB SLAVE or USB HOST10. Lead out 68 GP10 (all lead out from PL end) (34 groups) all connected in pairs with differential lines, and the differential lines are of equal length One side of the BANK is independently powered, and the BANK voltage can be adjusted by resistors Gigabit Ethernet (connected to PL end) output interface SP: 1.47-inch vertical screen (172X320) or SP2: 1.3-inch square screen (240x240) (connected to PL end) PL is connected to 50M active crystal oscillator , USB and downloader are all connected to ESD electrostatic protection devices 8-layer immersion gold board can run Color: As Shown Material: Metal Package Contents: 1set x Minimum System Development Board Only the above package content, other products are not included. Note: Light reflection and different displays may cause the color of the item in the picture a little different from the real thing. The measurement allowed error is +/- 1-3cm.